1. Field of the Invention
The present invention relates to a system for demodulating digital data. More particularly, the present invention improves the synchronization resolution timing for a class of digital data demodulators that use a training sequence, or preamble, to synchronize the demodulator's symbol sampling timing with the received signal's symbol timing. The system exploits the relationships among correlation values to determine if a fractional sample delay is to be inserted in the demodulator's symbol sampling timing. The system also determines how much of a fractional sample delay should be used, and then it implements the delay.
2. Description of the Related Art
When modulated data is transmitted and received, the timing of the transmitter and the receiver are arbitrary. The quality of the demodulated data is dependent upon the ability to synchronize the demodulator's symbol sampling timing with the symbol timing of the received signal. Intersymbol interference (ISI) occurs when the demodulator's symbol sampling timing is not perfectly aligned (synchronized) with the symbol timing of the received signal. This ISI results in errors in the demodulation process and reduces the quality of the demodulated data.
In certain known digital data demodulators, it is useful for the received data to contain a training sequence, or preamble, which “trains” the demodulator on the important characteristics of the signal. The training sequence increases the quality of the demodulation process by synchronizing the demodulator's symbol sampling timing with the received signal's symbol timing, thereby decreasing the effect of ISI. Therefore, demodulators are often implemented using a sampling rate of N signal samples per data symbol so that the demodulator's symbol sampling timing can be synchronized on any of the N samples. Thus, when the sample nearest to the ideal timing is chosen, the demodulation timing will always be accurate to within +/−1/(2N) of a symbol period.
As larger values of N are used to increase the sampling rate, the timing resolution available increases, and the amount of ISI due to imperfect symbol sampling timing becomes negligible. However, as the sampling rate N is increased, the processing load also is increased, which generally increases the hardware requirements for performing the processing. Therefore, the designer must trade the increase in demodulator performance made possible by increasing the sampling rate N against the resulting increase in implementation complexity and cost.
There is a need, therefore, to provide a system capable of increasing the synchronization resolution timing without a corresponding increase in complexity and cost.